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mos integrated circuit m m m m pd16654 150/154 output tft-lcd gate drive 1998 ? document no. s11647ej1v0ds00 (1st edition) date published may 1998 n cp(k) printed in japan data sheet the m pd16654 is a tft-lcd gate driver. because this gate driver has a level shift circuit for logic input, it can output a high gate scanning voltage in response to a cmos-level input. moreover, it can also drive both the xga/sxga panel (154 outputs) and svga panel (150 outputs) by changing the number of outputs over between 150 and 154. features ? high breakdown voltage output (on/off range: v dd2 -v ee2 = 40 v max.) ? 3.3 v cmos level input ? number of output select function (150/154 outputs) ordering information part number package m pd16654n- tcp (tab package) the tcps external shape is customized. to order your tcps external shape, please contact an nec salesperson.
2 m m m m pd16654 1. block diagram ls r/l ls osel ls clk ls stvr ls o e1 ls o e2 ls o e3 sr1 sr2 sr3 154-bit shift register sr152 sr153 sr154 ls stvl o 1 o 2 o 3 o 152 o 153 o 154 ls (level shifter): interfaces between 3.3 v cmos level and v dd2 -v ee1 level.
3 m m m m pd16654 2. pin configuration ( m m m m pd16654n- ) v dd2 stvl o e1 o e2 o e3 clk r/l v cc osel v ss stvr v ee1 v ee2 s 154 s 153 s 152 s 151 s 4 s 3 s 2 s 1 (cupper plated surface) caution this figure does not specify the tcp package.
4 m m m m pd16654 3. pin functions pin symbol pin name description o 1 to o 154 driver output pins scan signal output pins that drive the gate electrode of a tft-lcd. the status of each output pin changes in synchronization with the rising edge of shift clock clk. the output voltage of the driver is v dd2 to v ee2 . stvr stvl start pulse input/output pin input/output pin of the internal shift register. start pulse signal is read at the rising edge of shift clock clk and a scan signal is output from the driver output pin. the interface of this terminal is cmos of 3.3 v. when o sel signal is low level, start pulse goes up to high level at the 154th falling edge of shift clock clk and goes down to low level at the 155th falling edge. and when o sel signal is high level, start pulse goes up to high level at the 150th falling edge of shift clock clk and goes down to low level at the 151st falling edge . the output level is v cc -v ss (logic level). clk shift clock input shift clock input for the internal shift register. the contents of internal shift register is shifted at the rising edge of clk. r/l shift direction switching input shift direction switching input pin of the internal shift register. r/l = h (right shift) : stvr ? o 1 ? o 2 o 153 ? o 154 ? stvl r/l = l (left shift) stvl ? o 154 ? o 153 o 2 ? o 1 ? stvr o e1 o e2 o e3 enable input this pin fixes the driver output to the l level when it is high. however, the shift register is not cleared. and, output enable actuation is asynchronous in the clock. and, refer to relations of enable input and output terminal. o sel number of output select input selects the number of outputs. o sel = l : 154 outputs (svga) o sel = h: 150 outputs (vga, xga, sxga) when o sel = h (150 outputs), o 76 through o 79 outputs of the shift register are fixed to the v ee2 level. fix this pin to v cc (v dd2 ) or v ss (v ee1 ) on tcp. v dd2 positive power supply for driver shared with internal logic and driver v cc reference power supply 3.3 v 0.3 v. reference power supply for level shifter: ls v ss ground (gnd) connect this pin to the system gr ound. v ee1 negative power supply for internal logic negative power supply for internal logic v ee2 negative power supply for driver negative power supply for driver caution 1. power on/off sequence to prevent the m m m m pd16654 from damage due to latch up, turn on power in the order v cc ? ? ? ? v ee1 , v ee2 and v dd2 ? ? ? ? logic input. turn off power in the reverse order. observe these power sequences even during transition period.
5 m m m m pd16654 caution 2. inserting bypass capacitor because the internal logic operates at a high voltage (v dd2 -v ee1 ), insert a bypass capacitor of about 0.1 m m m m f between the respective power pins as shown below to secure the noise margin of v ih and v il . 0.1 f m 0.1 f m 0.1 f m 0.1 f m v dd2 v cc v ss v ee2 v ee1 do not input a switching signal to the o sel pin that selects the number of outputs. connect this pin to v cc or v ss (v ee1 ).
6 m m m m pd16654 4. relations of enable input and output terminal switching is possible for 154/150 with m pd16654 by the o sel terminal. and, the output terminal which can be controlled by the enable signal changes as follows along with this function. 154 out tcp 150 out mode 154 out mode (o sel = l) 150 out mode (o sel = h) 154 out mode (o sel = l) 150 out mode (o sel = h) o 1 (o e1 )o 1 (o e1 )o 1 (o e1 )o 1 (o e1 ) o 2 (o e2 )o 2 (o e2 )o 2 (o e2 )o 2 (o e2 ) o 3 (o e3 )o 3 (o e3 )o 3 (o e3 )o 3 (o e3 ) o 4 (o e1 )o 4 (o e1 )o 4 (o e1 )o 4 (o e1 ) o 5 (o e2 )o 5 (o e2 )o 5 (o e2 )o 5 (o e2 ) o 6 (o e3 )o 6 (o e3 )o 6 (o e3 )o 6 (o e3 ) ? ? ? ? ? ? ? ? ? ? ? ? o 72 (o e3 )o 72 (o e3 )o 72 (o e3 )o 72 (o e3 ) o 73 (o e1 )o 73 (o e1 )o 73 (o e1 )o 73 (o e1 ) o 74 (o e2 )o 74 (o e2 )o 74 (o e2 )o 74 (o e2 ) o 75 (o e3 )o 75 (o e3 )o 75 (o e3 )o 75 (o e3 ) o 76 (o e1 )v out = v ee2 o 77 (o e2 )v out = v ee2 o 78 (o e3 )v out = v ee2 o 79 (o e1 )v out = v ee2 o 80 (o e2 )o 80 (o e1 )o 80 (o e2 )o 80 (o e1 ) o 81 (o e3 )o 81 (o e2 )o 81 (o e3 )o 81 (o e2 ) o 82 (o e1 )o 82 (o e3 )o 82 (o e1 )o 82 (o e3 ) ? ? ? ? ? ? ? ? ? ? ? ? o 150 (o e3 )o 150 (o e2 )o 150 (o e3 )o 150 (o e2 ) o 151 (o e1 )o 151 (o e3 )o 151 (o e1 )o 151 (o e3 ) o 152 (o e2 )o 152 (o e1 )o 152 (o e2 )o 152 (o e1 ) o 153 (o e3 )o 153 (o e2 )o 153 (o e3 )o 153 (o e2 ) o 154 (o e1 )o 154 (o e3 )o 154 (o e1 )o 154 (o e3 )
7 m m m m pd16654 5. timing chart (1) 154 outputs, r/l = h o sel = l clk o e1 o e2 o e3 stvr o 1 o 2 o 3 o 153 o 154 stvl o 1 of next stage o 2 of next stage 1 2 3 153 154 155 156 157
8 m m m m pd16654 (2) 150 outputs, r/l = h o sel = h clk o e1 o e2 o e3 stvr o 1 o 2 o 3 o 153 o 154 stvl o 1 of next stage o 2 of next stage 2 3 149 150 151 152 153 1 o 76 to o 79 is l (v ee2 ) level fixation (150 output).
9 m m m m pd16654 6. electric specification absolute maximum ratings (t a = 25c, v ss1 = v ss2 = 0 v) parameter symbol rating unit supply voltage v dd2 C0.5 to +28 v supply voltage v cc C0.5 to +7.0 v supply voltage v dd2 -v ee1/2 C0.5 to 42 v supply voltage v ee1 C16.5 to +0.5 v supply voltage v ee2 v ee1 C 0.5 to +0.5 v input voltage v i C0.5 to v cc + 0.5 v input current i i 10 ma output current i o 10 ma operating temperature range t a C20 to +70 c storage temperature range t stg C55 to +125 c recommended operating condition (t a = C20 to +80c, v ss1 = v ss2 = 0 v) parameter symbol min. typ. max. unit supply voltage v dd2 17 25 v supply voltage v ee1 C15 C5.0 v supply voltage v ee2 v ee1 v ee1 + 6.0 v supply voltage v dd2 C v ee1 22 40 v supply voltage v cc 3.0 3.3 3.6 v electrical specifications (t a = C20 to +70c, v dd1 = 25 v, v dd2 = 3.3 v 0.3 v, v ee1 = v ee2 = C15 v, v ss = 0 v) parameter symbol condition min. typ. max. unit input voltage, high v ih 0.8 v cc v cc v input voltage, low v il clk, stvr (stvl), r/l, o sel , o e1 -o e3 v ss 0.2 v cc v output voltage, high v oh stvr (stvl), i oh = C40 m a v cc C 0.4 note v cc note v output voltage, low v ol stvr (stvl), i ol = +40 m a v ss note v ss + 0.4 note v output current, high i noh on, vn = v dd2 C 1.0 v C1.0 ma output current, low i nol on, vn = v ee2 + 1.0 v 1.0 ma output on resistance r on vn = v ee2 + 1.0 v or v dd2 C 1.0 v 1.0 k w input leakage current i il v i = 0 v or 3.6 v 1.0 m a i dd2 v dd2 , f clk = 30 khz, no loads 400 m a i cc v cc1 , f clk = 30 khz, no loads 600 m a dynamic current i ee i ee1 + i ee2 , f clk = 30 khz, no loads 800 m a note the cascade output is at the driver level (v cc -v ss ).
10 m m m m pd16654 switching characteristics (t a = C20 to +70c, v dd1 = 25 v, v dd2 = 3.3 v 0.3 v, v ee1 = v ee2 = C15 v, v ss = 0 v) parameter symbol condition min. typ. max. unit t phl1 800 ns cascade output delay time t plh1 c l = 20 pf clk ? stvl (stvr) 800 ns t phl2 500 ns driver output delay time 1 t plh2 c l = 300 pf clk ? on 500 ns t phl3 500 ns driver output delay time 2 t plh3 c l = 300 pf o en ? on 500 ns t tlh 450 ns output rise time output fall time t thl c l = 300 pf 450 ns input capacitance c i t a = 25c 15 pf maximum clock frequency f max. when connected in cascade 500 khz timing requirement (t a = C20 to +70c, v dd1 = 25 v, v dd2 = 3.3 v 0.3 v, v ee1 = v ee2 = C15 v, v ss = 0 v) parameter symbol condition min. typ. max. unit clock pulse low period pw clk(h) 500 ns clock pulse high period pw clk(l) 500 ns enable pulse low period pw oe 1.0 m s data setup time t setup stvr (stvl) - ? clk - 200 ns data hold time t hold clk - ? stvr (stvl) 200 ns the rise and fall times of logic input must be t r = t f = 20 ns (10% to 90%).
11 m m m m pd16654 7. switching characteristics waveform (r/l = h) clk v cc v ss stvl1/2 (stvr1/2) v cc v ss stvr1/2 (stvl1/2) v cc v ss oe n v cc v ss o n v dd2 v ee2 1/f max. pw clk(h) pw clk(l) 50% 50% 50% 50% t setup t hold 50% 50% t plh1 t phl1 50% 50% t plh2 t tlh t phl2 t thl 90% 90% 10% 10% pw oe 50% 50% t plh3 t phl3 90% 10% o n v dd2 v ee2 v ee1 v ee1 v ee2
12 m m m m pd16654 8. recommended mounting conditions when mounting this product, please make sure that the following recommended conditions are satisfied. for packaging methods and conditions other than those recommended below, please contact nec sales personnel. mounting condition mounting method condition soldering heating tool 300 to 350c, heating for 2 to 3 sec; pressure 100 g (per solder) thermocompression acf (adhesive conductive film) temporary bonding 70 to 100c; pressure 3 to 8 kg/cm 2 ; time 3 to 5 sec. real bonding 165 to 180c; pressure 25 to 45 kg/cm 2 , time 30 to 40 secs. (when using the anisotropy conductive film sumizac1003 of sumitomo bakelite, ltd.) caution to find out the detailed conditions for packaging the acf part, please contact the acf manufacturing company. be sure to avoid using two or more packaging methods at a time. reference nec semiconductor device reliability/quality control system (c10983e) quality grades to necs semiconductor devices (c11531e)
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m m m m pd16654 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96. 5

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